1. Field of the Invention
This invention relates, in general, to digital signal processing systems and, more specifically, to input-output buffers for interfacing a digital signal processing system with data acquisition devices.
2. Description of the Prior Art
In signal processing systems, special purpose digital signal processors have been used to process digital data words representative of a series of data points of an electrical analog signal. One such digital signal processor, disclosed in U.S. Pat. No. 3,812,470, issued to J. Murtha and J. Ross and assigned to the assignee of the present invention, is designed to efficiently perform a Fast Fourier Transform on a block of data words.
A typical approach to improve the throughput of a signal processor utilizes a so-called input-output or storage controller which independently handles the transfer of data between the central processing unit and the input-output devices thereby relieving the central processor of the time consuming task of communicating with each device.
However, input-output controllers transfer a block of data, word-by-word, to the central processing unit. Although it is known to utilize buffers or holding registers to temporarily store each word transferred between two devices, such as an input-output controller and the central processing unit, to thereby allow for the differences in the data rates of the two devices, such a method decreases the overall throughput of the digital processing system since both the input-output controller and the central processing unit are locked together during the transfer of the block of data words which prevents each device from processing other data during the transfer of a block of data between the two devices.
Thus, it would be desirable to provide input-output buffers which are capable of storing a complete vector or block of data words that are to be transferred between an input-output controller or other data acquisition device and a digital signal processor. It is also desirable to provide input-output buffers which operate independently of both the input-output controller and the digital signal processor such that a vector of data may be transferred into or out of one of the buffers from the input-output controller or the digital signal processor at the same time that the input-output controller or signal processor, not involved in the transfer of a vector of data words to the buffer, is processing other data.